A semiconductor device constructed with an insulated gate transistor and an anti-parallel diode that are formed in a common semiconductor substrate is disclosed, for example, in US 2005/0258493 corresponding to Japanese Patent Publication No. 2005-317751, US 2007/0108468 corresponding to Japanese Patent Publication No. 2007-134625, and US 2007/0170549 corresponding to Japanese Patent Publication No. 2007-214541.
FIG. 19 illustrates a semiconductor device 100 disclosed in US 2007/0170549. In the semiconductor device 100, an insulated gate bipolar transistor (IGBT) cell 100i and a diode cell 100d are formed in a common semiconductor substrate 1. A first electrode layer 8 made of polysilicon is formed in a first trench T1 through an insulation film 7. The first electrode layer 8 serves as a gate electrode of the IGBT cell 100i. A second electrode layer 10 made of aluminum is formed on a first side of the semiconductor substrate 1. A second trench T2 is filled with the second electrode layer 10. The second electrode layer 10 penetrates through a first side N-type region 3a and a first side P-type region 4a so that the first side N-type region 3a and the first side P-type region 4a can be electrically coupled. Further, the second electrode layer 10 is electrically coupled to a P-type layer 2a. The second electrode layer 10 serves as an emitter electrode of the IGBT cell 100i and an anode electrode of the diode cell 100d. A second side P+-type region 5 and a second side N+-type region 6 are formed to a surface portion of a second side of the semiconductor substrate 1. A third electrode layer 11 is formed on the second side of the semiconductor substrate 1 and electrically coupled to each of the second side P+-type region 5 and the second side N+-type region 6. Thus, the second side P+-type region 5 and the second side N+-type region 6 are electrically coupled by the third electrode layer 11. The third electrode layer 11 serves as a collector electrode of the IGBT cell 100i and a cathode electrode of the diode cell 100d. 
That is, in the semiconductor device 100, an insulated gate transistor and a diode are coupled together in an antiparallel configuration. A first terminal (e.g., collector) of the insulated gate transistor and a cathode of the diode are coupled together at a high potential side, and a second terminal (e.g., emitter) of the insulated gate transistor and an anode of the diode are coupled together at a low potential side. Such a semiconductor device as the semiconductor device 100 is usually integrated in an inverter circuit to control an electrical load by a pulse width modulation (PWM) technique.
Generally, when such a semiconductor device as the semiconductor device 100 is used in an inverter circuit, a gate signal applied to an IGBT of an upper half of the inverter circuit is opposite in phase with a gate signal applied to an IGBT of a lower half of the inverter circuit. Therefore, the gate signal may be applied to the IGBT even during a freewheel operation of a diode coupled to the IGBT in an antiparallel configuration. That is, there may be a period of time when the IGBT and the diode operate at the same time. As described above, in the semiconductor device 100, the collector of the IGBT and the cathode of the diode are coupled together, and the emitter of the IGBT and the anode of the diode are coupled together. Therefore, when the IGBT is turned on, the cathode and anode of the diode try to be at the same potential. As a result, a forward bias voltage of the diode rises, and a forward loss of the diode increases accordingly. In this way, in the semiconductor device 100 shown in FIG. 19, the forward loss of the diode may be increased due to the fact that the IGBT and the diode interfere with each other.
The present inventor has studied a semiconductor device 90 illustrated in FIG. 20 (Japanese Patent Application No. 2007-229959). The semiconductor device 90 is configured to avoid interference between an IGBT and a diode so that an increase in a forward loss of the diode can be prevented.
As shown in FIG. 20, the semiconductor device 90 includes an AND circuit 50, an IGBT 20 with a built-in diode, a sensing resistor 30, and a feedback circuit 40.
The AND circuit 50 is a logic gate that produces a high level output only when all inputs are high level. A PWM gate signal for driving the IGBT 20 is inputted to the AND circuit 50 from an external circuit. Further, an output of the feedback circuit 40 is inputted to the AND circuit 50.
The IGBT 20 includes an IGBT section 21 and a diode section 22. The IGBT section 21 and the diode section 22 are formed in a common semiconductor substrate. The IGBT section 21 includes a primary IGBT 21a coupled to an electrical load and a secondary IGBT 21b for detecting an electric current flowing through the primary IGBT 21a. Voltages applied to the gates of the IGBTs 21a, 21b are controlled by the PWM gate signal outputted from the AND circuit 50. An emitter of the secondary IGBT 21b is coupled to a first end of the sensing resistor 30, and a voltage drop Vs across the sensing resistor 30 is fedback to the feedback circuit 40. The diode section 22 is configured to commutate a load current flowing through the IGBT 21a. The diode section 22 includes a primary diode 22a coupled to the primary IGBT 21a and a secondary diode 22b for detecting an electric current flowing through the primary diode 22a. An anode of the secondary diode 22b is coupled to the first end of the sensing resistor 30.
The feedback circuit 40 determines whether the electric current flows through the primary diode 22a and also determines whether an excessive current flows through the IGBT 21a. Based on results of the determinations, the feedback circuit 40 allows or prevents the PWM gate signal to pass through the AND circuit 50. Specifically, when the primary IGBT 21a is driven, the feedback circuit 40 outputs to the AND circuit 50 a signal that allows the PWM gate signal to pass through the AND circuit 50. However, if voltage drop Vs across the sensing resistor 30 is less than a diode current detection threshold Vth1 or greater than a excessive current detection threshold Vth2, the feedback circuit 40 outputs to the AND circuit 50 a signal that prevents the PWM gate signal to pass through the AND circuit 50.
Thus, in the semiconductor device 90 illustrated in FIG. 20, the primary diode 22a conducts the electric current in the forward direction without interfering with the primary IGBT 21a. Therefore, an increase in a forward voltage of the primary diode 22a is avoided, and an increase in a forward loss of the primary diode 22a can be prevented accordingly.
Further, if the excessive current flows through the primary IGBT 21a, the feedback circuit 40 outputs to the AND circuit 50 the signal that prevents the PWM gate signal to pass through the AND circuit 50. Thus, the IGBT 21a can be protected from the excessive current.